library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity MyCounter is
	port (Clock, Reset : in STD_LOGIC;
	      Counter      : out STD_LOGIC_VECTOR(7 downto 0));
end entity;

architecture RTL of MyCounter is
begin
	process
		variable InternalCounter : UNSIGNED(7 downto 0);
	begin
		wait until RISING_EDGE(Clock);

		-- Increase the counter with each clock.
		-- Stop at 255.

		if Reset = '1' then
			InternalCounter := (others => '0');
		elsif InternalCounter /= 255 then
			InternalCounter := InternalCounter + 1;
		end if;

		Counter <= STD_LOGIC_VECTOR(InternalCounter);
	end process;

end architecture;