library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;

entity MyCounter_tb is
end entity;

architecture RTL of MyCounter_tb is
	signal Clock, Reset : STD_LOGIC;
	signal Counter : STD_LOGIC_VECTOR(7 downto 0);
begin
	the_counter : entity MyCounter
		port map(Clock => Clock,
		         Reset => Reset,
		         Counter => Counter);

	-- Generate the clock:

	process
		variable Iterations : Integer;
	begin
		-- Reset the counter:

		Reset <= '1';
		Clock <= '0';
		wait for 100 ns;
		Clock <= '1';
		wait for 100 ns;

		Reset <= '0';

		-- Start the clock:

		Iterations := 0;

		while Iterations < 300 loop
			Clock <= '0';
			wait for 100 ns;
			Clock <= '1';
			wait for 100 ns;

			Iterations := Iterations + 1;
		end loop;

		-- Stop the clock.
		wait;
	end process;

end architecture;

-- Simple configuration

configuration MyCounter_test of MyCounter_tb is
	for RTL
	end for;
end configuration;